April, 8th, 2008

“High-speed clock and data recovery”

Chairman: Prof. Michiel Steyaert (KU Leuven)

Time 
Title/Author(s)
08.45-09.10  Welcome and Opening
09.15-10.00 Anthony Sanders, Infineon
Fundamental Stochastic Jitter Processes associated with Clock and Data Recovery: A Tutorial
10.00-10.45 Massimo Pozzoni, STMicroelectronics
Clock Recovery and Equalization Techniques for Lossy Channels in Multi Gb/s Serial Links
10.45-11.15 COFFEE-BREAK
11.15-12.00 J.Crols, AnSem
Top-down bottom-up design methodology for fast and reliable Serdes developments in nm technologies
12.30-12.45 Michael Perrott, MIT
Mixed-Signal Implementation Strategies for High Performance Clock and Data Recovery Circuits
12.45-14.00 LUNCH
14.00-14.45 Song Wu, Xilinx
Jointly Optimize Equalizer and CDR for Multi-gigabits SerDes
14.45-15.30 J.Daniels, KU Leuven
Time-to-digital conversion: an alternative view on synchronisation
15.30-16.00 COFFEE-BREAK
16.00-17.00 Panel Discussion with all Speakers
17.00-18.00 Visit to Volta Museum
19.30 Social dinner
 
   Pavia,