International Conference on IC Design and Technology

Keynote Speakers

Keynote Speakers

Alek Dediu
CNR, Italy

Molecular Spinterface – From Fundamentals to Applications

Information and communication technology (ICT) is calling for solutions enabling lower power consumption, further miniaturization and multi-functionality requiring the development of new device concepts and new materials. A fertile approach to meet such demands is the introduction of the spin degree of freedom into electronics devices, an approach commonly known as spintronics. This already lead to a revolution in the information storage (GMR read heads) in the last decades. Nowadays, the challenge is to bring spintronics also into devices dedicated to logics, communications and storage within the same material technology.
Organic semiconductors emerged as an extraordinary spintronic material about ten years ago, when a few papers appeared with straightforward and encouraging claims on spintronics phenomena. From then on Organic Spintronics has evolved into a prolific discipline populated by a large number of experimentalists and theoreticians.
This lecture will discuss the multi-functionality as an intrinsic characteristic of organic based spintronic devices leading to conceptually new device paradigms. Along this line I will especially concentrate on interfaces, representing the most important and the most hidden part of any spintronic device. Revealing their secrets is scientifically hard and experimentally costly, requiring sophisticated spectroscopic methods and massive calculations. For an interface consisting of a hard metallic electrode touching a soft organic layer, the situation obviously becomes even more complicated. The lecture will overview the main achievements of the community in the investigation of very complex and very rich interface properties and will describe the possibilities to develop and fabricate devices whose operation is fully dominated by the interface.

Valentin Alek Dediu is leader of the spintronic group at the Institute of Nanostructured Materials, Italian National Council of Research. He received a diploma in experimental physics in 1982 and accomplished his Ph.D. on superconductivity in 1989 both at the Moscow Physical-Engineering University. Alek Dediu pioneered in the early 2000 the first experimental evidences on molecular spintronics and in the 2010-2015 period contributed to the development of the spinterface concept, the most advanced achievement of the molecular spintronics. His main research interests are: molecular spintronics, interface physics and quantum engineering, memristive properties and neuromorphic computing, nanomagnetism for medical applications and others.

Paolo Cappelletti
STMicroelectronics, Italy

Is Now the Time for Emerging Non-Volatile Memories?

For different reasons, both stand-alone and embedded Non-Volatile Memories are at a turning point. NAND Flash dominates stand-alone NVM arena, as far as market size and bit-volumes. NAND has also become the highest density and lowest cost memory technology, overtaking DRAM in the technology-scaling race. Facing increasing difficulties in further scaling planar technology, NAND has already undertaken a revolutionary transition to 3-D integration, prolonging the roadmap of cost reduction and density increase for some more years. NAND transition to 3-D integration is further enlarging the performance gap between DRAM and NVMs, opening opportunities for emerging memories to fill the gap.
The embedded NVM picture is much more complex because of the variety of applications, business models and technical solutions. In principle, this should have been an easier field for emerging NVMs to start playing a role. In reality, embedded NVM chip providers and end users are quite conservative and there has not been so far a compelling reason to abandon conventional solutions. However, digital technologies have also undertaken a revolutionary change with the introduction of high K metal gate CMOS transistors and, even more, with the transition to fully depleted SOI and to FinFETs. Integrating conventional NVM cells in advanced CMOS technologies is becoming more and more difficult and costly; that is giving emerging NVM a great opportunity to take-off.
The presentation will analyze the scenarios of stand-alone and embedded NVM, focusing on the opportunities for emerging NVMs in both fields, and it will discuss how realistic is that one or more of the different new memories will actually emerge from the incubation phase to become a technology of industrial relevance.

Paolo Cappelletti received the Laurea degree in Physics from the University of Milan, Italy, in 1978. In 1979, he joined the VLSI Process Development Group of SGS, now STMicroelectronics. Until 1984 he was engaged in NMOS process integration and from 1984 to 1986, he led the DRAM technology development.  Since 1986 he has been working on Non Volatile Memories: until 1990 he led the development of CMOS technologies for EEPROM's and embedded NVM, in the 90’s he focused his activity on Flash memories and, since 1998, he was responsible for the development of all NVM technologies. In 2008, when Intel and STMicroelectronics created Numonyx, he joined the new company as V. P. of Technology Development, in the R&D Technology Center of Agrate Brianza, Italy; after Numonyx acquisition, he became part of Micron Process R&D staff as Process Integration Senior Director, managing the development and the 200 to 300mm transition of NOR and PCM technologies. Since 2016 Paolo Cappelletti has rejoined STMicroelectronics as Non Volatile Memory Company Fellow. He has authored or co-authored over 40 technical papers and the book “Flash memories”, edited by Kluwer Academic Publishers in 1999; he has been invited speaker at international conferences and he served in technical committees for IEDM and ESSDERC. He is holding over 50 patents in the field of Integrated Circuits and Non Volatile Memories.

Stefano Scaldaferri and Francesco Dalena
Dialog Semiconductor, Italy


Advanced Charger Architectures for Mobile Applications

Battery capacity is steadily rising to accommodate the constant increase of power demand of modern mobile systems applications while at the same time extending system runtime.
Reducing charge time is a key target of state-of-the-art charger systems. Modern travel adapter and connectors allows to deliver higher power (Power Delivery, USB Type C connector, Quick Charge and Fast Charging protocol) and at the same time advancements in battery technology enable >1C charge current (Silicon/Graphene LiIon technology). While those developments enable charging with higher current levels, this poses unprecedented challenges to integrated charger circuits which need to guarantee this power transfer while staying below thermal and size constraints of modern mobile systems.
This keynote starts from a general introduction on standard charging circuits and KPI to into a detailed overview of modern charger systems topologies, where tradeoffs and design implications will be analyzed in detail.

Stefano Scaldaferri received his M.Sc. Degree in Electronic Engineering from the University of Pisa in 2003. He specialized with a Master in Engineering of Embedded System Design from the University of Lugano in 2004. He joined Infineon Technologies, Munich in September 2004, where he worked as mixed signal design engineer on low noise, low-voltage sense amplifiers and high speed data path architectures for DDR DRAMS. He joined Dialog semiconductor, Munich in September 2006, working on chargers and DC/DC converter and leading the development of 3 PMICs for high volume mobile applications. Since January 2013 he is Engineering Director of Dialog Semiconductor Italy leading a team of 70+ Engineers on the development of Charger and PMICs for mobile applications with >3 ICs brought into volume production. He holds 5 US patents and 2 Technical publications.

Francesco Dalena received his M. Sc. Degrees in Electronic Engineer from Polytechnic of Bari in 2001. From 2000 to 2001 he joined Alcatel Microelectronics in Milan to develop the thesis on a 14 bits pipeline A/D converter for xDSL. From 2002 to 2006 he worked as Analog & Mixed Signal designer at STMicroelectronics in Lecce and Milan design centers designing the first three axis accelerometer, gyroscope and pressure sensor based on MEMS technology. From 2006 to 2008 he worked as Member of Technical Staff at MAXIM Integrated Products in Milan designing power management IC for Power over Ethernet and Hot Swap products. From 2008 to 2012 he worked as CTO with Le Gemme leading advanced electronic systems projects for military and industrial applications. In 2013 he joined Dialog Semiconductor in Livorno working on DC/DC converter, Energy Harvesting and PMIC for portable applications. He holds 4 US patents (other 4 pending ) and 10 technical publications. His interests include switch mode power supply, power management, analog, mixed signals, sensor and communication systems.

Francesco Brandonisio
Infineon Technologies, Austria

Time-Mode Signal-Processing and its Impact on Products: the Past, Present and Future

Time-mode signal processing comprises all those circuits in which information is (i) associated with the duration of time intervals and (ii) processed by changing those durations. Time-mode is a compelling alternative to the traditional, well established,  voltage- and current- mode signal processing.
In this talk, we show advantages and challenges of time-mode circuit design. We give an overview of the main time-mode building blocks published in the literature so far. We identify the missing blocks and define possible trends for the future.

Francesco Brandonisio received his B. Sc and M. Sc. degrees in engineering from Politecnico of Bari, Italy, in 2004 and 2006, respectively. In 2006/2007, he worked on 3D imaging systems in Sirtexsoa and Politecnico di Bari. He started a Ph. D. program in Microelectronics in University College Cork and Tyndall National Institute, Ireland, in 2007 and received the Ph. D. degree in 2012. His Ph.D. topics are digital Phase-Locked Loops (PLLs), Time-to-Digital converters (TDCs) and injection locking. He was a postdoctoral researcher from 2012 to 2014 in Tyndall National Institute and Microelectronic Center Ireland on digital PLLs and TDCs. He worked in ON-Semiconductor on DC-DC converters, Limerick, Ireland in 2015. In the last 2 years, he has been working on digital PLLs in the Clock and Interface Systems group in Infineon Technologies AG, Villach, Austria. He is author of the book “Noise-Shaping All-Digital Phase-Locked Loops: Modeling, Simulation, Analysis and Design”, Springer, January, 2014.